1. Field
The present application generally relates to device under test (DUT) arrays, and, more particularly, to a layout for DUT arrays used in semiconductor wafer level testing.
2. Description of Related Art
To assist in evaluating and/or controlling a semiconductor fabrication process, integrated circuit devices are fabricated on a wafer as test devices. These test devices are referred to as devices under test (DUTs). Typically, a wafer with DUTs formed thereon is positioned within a wafer tester. The wafer tester has an array of probes that make electrical contact with contact pads for the DUTs on the wafer. The wafer tester then performs electrical testing of the DUTs.
Typically, each DUT on a wafer has one or more contact pads assigned to it. Thus, in order to test all the DUTs on the wafer, the wafer tester has to either have enough probes to make contact with all the contact pads of all the DUTs on the wafer or test groups of DUTs at a time. Thus, the number of DUTs on a wafer can be limited by the number of DUTs that can be tested within a reasonable amount of time using the wafer tester.
A variety of arrays of DUTs are in use today. For example, a CMOS device array for determining the variability of the drive current is disclosed in Ohkawa, S., Aoki, M., Masuda, H., “Analysis and Characterization of Device Variations in an LSI Chip Using an Integrated Device Matrix Array”, Proc. International Conference on Microelectronic Test Structures (ICMTS), pp 70-75, 2003, which is incorporated by reference herein. However, in this array, the DUTs are measured in sequence, which is very slow. Also, device parameters like the threshold voltage cannot be measured due to the large array size. Furthermore, this approach cannot be ported into a scribe line.
Another array of various DUTs is disclosed in Leffers, R., Jakubiec, A., “An Integrated Test Chip for the Complete Characterization and Monitoring of a 0.25 um CMOS Technology that fits into five scribe line structures 150 um by 5000 um”, Proc. International Conference on Microelectronic Test Structures (ICMTS), pp 59-63, 2003, which is incorporated by reference herein. This array, however, requires a customized probe card with an operational amplifier connected to certain pins. Additionally, all measurements are done in sequence and there are force and sense pads required for both source and drain.
Another array of CMOS devices is disclosed in Quarantelli, M., Saxena, S., Dragone, N., Babcock, J. A., Hess, C., Minehane, S., Winters, S., Chen, J., Karbasi, H., Guardiani, C., “Characterization and Modeling of MOSFET Mismatch of a Deep Submicron Technology”, Proc. International Conference on Microelectronic Test Structures (ICMTS), Monterey (USA), 2003, which is incorporated by reference herein. In this array, there are selection devices on the drain path, which increases routing resistance significantly, and there will be a noticeable voltage drop if multiple devices are measured in parallel to save test time. Similar limitations exist for the CMOS device array disclosed in Saxena, S., Minehane, S., Cheng, J., Sengupta, M., Hess, C., Quarantelli, M., Kramer, G. M., Redford, M., “Test Structures and Analysis Techniques for Estimation of the Impact of Layout on MOSFET Performance and Variability”, Proc. International Conference on Microelectronic Test Structures (ICMTS), Hyogo (Japan), 2004, which is incorporated by reference herein. Additionally, these arrays do not fit into a scribe line, as may be desired.
An array of bipolar devices is disclosed in Einfeld, J., Schaper, U., Kollmer, U., Nelle, P., Englisch, J., Stecher, M., “A New Test Circuit for the Matching Characterization of npn Bipolar Transistors”, Proc. International Conference on Microelectronic Test Structures (ICMTS), Hyogo (Japan), 2004, which is incorporated by reference herein. In this array, there are selection devices to all DUT pins (in this case base, emitter and collector) and measurements are executed in sequence, which is a slow process.
Another array of CMOS used to determine parameter variation of devices is disclosed in Schaper, U., Einfeld, J., Sauerbrey, A., “Parameter Variation on Chip Level”, Proc. International Conference on Microelectronic Test Structures (ICMTS), pp 155-158, 2005, which is incorporated by reference herein. In this array, each transistor is addressed by a decoder and measured individually in sequence.
In addition, there are also SRAM or ROM based arrays disclosed in DeBord, J. R. D., Grice, T., Garcia, R., Yeric, G., Cohen, E., Sutandi, A., Garcia, J., Green, G., “Infrastructure for Successful BEOL Characterization and Yield Ramp at the 65 nm Node and Below, Proc. IITC 2005, which is incorporated by reference herein. These arrays, however, are not used to extract variation of device related parameters like drive current or threshold voltage.